1. Field of the Invention
This invention relates to frequency doubler and multiplier circuits.
2. Prior Art
Frequency doublers and multiplier circuits are widely employed in integrated-circuit designs to increase the frequency of an off-chip reference clock signal for internal use within the integrated circuit, primarily in application specific integrated-circuits (ASIC) and in microprocessor designs. In general, ASIC's are designed to be scalable such that they can be transferred into a new fabrication process, or technology, with low, or virtually no design and layout modification. The main purpose of having scalable designs is to reduce the so called "time to market window" and to lower product development costs. Thus, embedded frequency doubler modules used in such applications are designed to be insensitive to use in various fabrication process technologies in order to prevent a design bottleneck which might affect fabrication or operation of an entire chip.
Integrated clock signal doublers with reduced sensitivity to fabrication process variations and to temperature fluctuations, with wide power supply voltage and input frequency ranges, i.e., 1.8-6 V and 0.10-50 MHz, have a number of applications in ASIC and microprocessor designs. Yet, in practice, frequency doublers are designed for a particular fabrication process technology with limited input frequency and power supply voltage ranges, i.e., 1-40 MHz and 5 V.+-.10%.
There are two common types of integrated clock doublers: Phase-Locked Loop (PLL) based clock doublers, and delay circuit based clock doublers. A PLL based clock doubler is generally used in high-speed applications that require accurate output clocks.
FIG. 1 shows a block diagram of a typical PLL-based clock doubler system 10, which includes a voltage controlled oscillator (VCO) 12, a charge pump and filter 14, a phase-frequency detector 16, and a frequency divider 18 connected as shown in the Figure. Typically, a PLL is operated at twice the needed frequency and its output is divided by two to produce a 50 percent duty cycle clock signal at the expense of additional die size and power loss. However, this approach is seldom used in high-speed PLL designs with VCOs operating at greater than 300 MHz due to fabrication process bandwidth limitations.
The main drawbacks of PLL based doublers are their sensitivity to power supply and fabrication process variations. Oftentimes, the PLL must be completely redesigned, or extensively modified, when the fabrication technology or the power supply voltage is changed. Thus, the circuit may not be easily scaled from an existing fabrication process into a new process technology or even operated with a new power supply voltage in the same fabrication process.
FIG. 2 shows a delay-line based clock doubler system 20 which uses a simple Exclusive-Or (XOR) gate 22, or alternatively an Exclusive-Nor (XNOR) gate, with a constant delay circuit, or delay line 24 for doubling the frequency of a clock signal. As shown in FIG. 3, both edges of the input signal V.sub.IN are used to trigger the rising (or falling for XNOR) edge of the output clock signal V.sub.OUT. But, the falling edge of V.sub.OUT is triggered by both the rising and falling edges of the output signal V.sub.A of the delay circuit, which is shifted in the time domain by T.sub.delay seconds with respect to V.sub.IN. The value of T.sub.delay is nominally set to T.sub.delay =T.sub.IN /4 (where T.sub.IN =1 /.function..sub.IN) in order to produce an output with 50 percent duty cycle.
Note that XOR gate 22 can be replaced by a XNOR gate 22A, if the output signal of the delay line 24 is inverted (V*.sub.A .function..sub.IN), the output of the XNOR gate is V.sub.OUT *(2 .function..sub.IN), where * designates an inverted signal.
Delay circuits are sensitive to temperature and fabrication process variations and are also heavily influenced by power supply voltage levels. If V.sub.IN has less than 50 percent duty cycle, then any change in T.sub.delay will produce frequency distortions for V.sub.OUT. But, if the duty cycle of V.sub.IN is fixed at 50 percent, then delay modulation will only cause duty cycle distortion for V.sub.OUT . Therefore, any variation in T.sub.delay can cause either duty cycle or frequency distortion for V.sub.OUT.
The performance of a delay based doubler can be improved by compensating for the effects of process, temperature, and power supply voltage. However, each of these variables is typically corrected separately from each other, which requires multiple correction circuits to rectify all inaccuracies. The penalty for obtaining these corrections is additional design complexity, as well as increased die size and increased power losses. Furthermore, the input frequency must be held constant in order to produce an output clock with a defined duty cycle. Any change in .function..sub.IN requires that the delay circuit be redesigned to maintain the desired duty cycle, unless duty cycle variations can be tolerated. The circuit fails to operate when T.sub.IN &lt;2T.sub.delay (.function..sub.IN &gt;1/2T.sub.delay). Hence, these doublers are not appropriate for any chip with variable input frequency clocks and tight duty-cycle requirements.
Consequently, a need exists for a frequency doubler or multiplier which has reduced sensitivity to fabrication processes and to temperature fluctuations and which can tolerate wide variations in power supply voltage levels and has a wide input frequency range.